Principal Engineer

Location: 226 Airport Parkway, Suite 595, San Jose, CA 95110

Hours: 40 hours/week

Duties:

In the rapid changing and competitive global environment, develop integrated circuit (IC) designs with advanced video algorithm and other video-specific intellectual property to improve high resolution picture quality of display images. Work closely with the marketing team on products to increase market share of video processing chip and improve image quality algorithm in higher display resolution than commercial display resolution. Use advanced level electrical and electronics engineering skill to achieve technology that provides better picture quality in a wide variety of display terminals. Duties include architecture design, RTL (Register Transfer Level) coding, simulation, synthesis, static timing analysis(STA) and transfer of RTL from ASIC(Application Specific Integrated Circuits) to FPGA (Field Programmable Gate Array) prototyping. This job also involves FPGA emulation and validation. Work with marketing team to define products driven by effective cost and performance. Address system-on-chip (SOC) architecture, integrated circuit design, display port, memory bus fabric, keystone correction algorithm, Motion Estimation and Motion Compensation (MEMC) algorithm, de-interlace algorithm, color enhancement and high dynamic range (HDR) enhancement. Develop low power methodology, including power estimation, power modeling, power trade-off, power optimization and power review. Possible travel to Shanghai (5%).

Requirements:

Master’s degree in electrical engineering or electronics engineering, plus 24 months of experience as ASIC Engineer, FPGA engineer, electrical engineer or IC design engineer. Acceptable related/alternative job titles and experience in the job offered or in these or other related/alternative job titles will be considered. The functional experience, not the job title, is determinative.

Experience must include 2 years of hands-on experience in the following: low power design flow, video processor knowledge such as motion estimation and motion compensation (MEMC), motion vector calculation (MVC), frame interpolation (FI), keystone correction, frame rate conversion (FRC), color management (CM), de-interlace (DI), display timing generator (DTG), mobile video processor with high resolution picture quality enhancement experience, bus protocols such as OCP, AXI, LVDS, MIPI, VYBONE, etc., arbiter, scheduling, synchronization, interconnection; C, C++ model debug and implementation, embedded software and hardware co-work experience, and FPGA platform HAPS debugging experience. Experience must also include 12 months of verification skills, such as SYSTEMMC, SYSTEMVERILOG, UVM, block and full chip verification. Experience may have been gained concurrently.