Senior/Staff FPGA Engineer


Location: Shanghai, China


  • FPGA design and verification. Porting ASIC code to FPGA platform, verify the whole design in FPGA system.
  • RTL module development to assist the verification on FPGA.
  • Solving and improving FPGA timing performance
  • Lead the whole FPGA verification flow, include specification, coding, simulation, physical implementation and board level debugging.
  • Setup the FPGA system peripheral board design requirement and lab test/measurement equipment (logic analyzer, oscilloscope, in-circuit emulator).
  • Capability of making rapidly scheme/method to trace issue.


  • BS with more than 8 years or MS with more than 5 years in Electronic or Computer Science Engineering is required.
  • More than 5 years’ experience in design and verify on FPGA. Expert in FPGA operation theory.
  • Strong digital logic design knowledge and FPGA internal and I/O timing constraint closure experience.
  • In-depth knowledge of FPGA synthesis/PAR tools (Proto-Compiler/Synplify/Vivado) and multiple FPGA platforms (preferably HAPS/ProDesign).
  • Experience with multiple FPGA partition application for large-scale SOC prototyping verification with related tools (Proto-Compiler/Certify)
  • Experience with high-speed signal peripheral IP/device verification with FPGA
  • Knowledge of FPGA HW co-emulation/UVM simulation is a plus.
  • Knowledge of script language (Perl/Python/tcl) is required.
  • Highly motivated, fast learner, team player with good oral/written Chinese/English communication skills