Senior / Staff STA Engineer

Apply Now

Location: Shanghai, China

Job Responsibilities:

• Working with design, synthesis and DFT team on development of timing constraints
• Working with physical design engineers on timing closure including timing analysis and eco analysis, signal integrity analysis

Minimum Qualifications:

• Very familiar of PrimeTime usage and timing closure methodologies
• Good timing constraint (SDC) development ability based on SoC chips design/timing requirement.
• Hands-on experience in timing closure of multiple complex SoC chips
• Capable to do final timing sign-off at whole chip level independently and proven tracking records of timing sign-offs
• Good understanding of CTS quality check
• Good understanding of physical design flow and their impact on timing closure
• Good at script language of TCL/Perl
• 3~5 years of work experience in STA
• Familiarity of RTL design is a plus
• Fluent in oral and written English

Education Requirements:

• Required: Bachelor's, Electrical Engineering
• Preferred: Master's, Electrical Engineering