Senior IC Engineer (b)

Location: Shanghai, China

Responsibilities:

• Independently handle key IC design tasks: Understanding the algorithm/protocol requirement and implementation with RTL
• Block level Micro-architecture, RTL coding
• Chip/block level verification debug
• Module and top level integration, including constraints definition, synthesis, power analysis and timing closure
• Support FPGA validation and Silicon bring-up
• Interface with 3rd party vendor for successful integration into SOC

Requirements:

• BSEE Degree or above
• About 3~5 years of experience in hands-on digital IC design
• Familiarity with ASIC design methodology and SoC implementation flow
• Familiarity with standard CAD tools including simulation, synthesis, formal verification tools
• Self-motivated in solving problems
• Good communication skills and fluent in English
• Good team player. A plus to have: Experience of image or video IP design
• Good scripting skills
• Knowledge of power and low power design