ASIC Architect Engineer

Location: Shanghai, China

Responsibilities:

• Working with marketing team to define the chip feature, partition the cost for each feature
• Estimate the chip cost in product define stage
• Define and break down the product requirement from system level, mapping the product feature to IP level
• Write fucntional spec for design team and verification team, review the IP design spec from IP owner and verification spec from verification owner
• Strongly C++ background is required:
  • Add debug dump/maintain existed C++ algorithm
  • Convert the floating-point C algorithm to fixed C++ version for RTL implementation
  • C-model for chip-level/IP block level maintain.
  • Created C/C++ model for chip component(like FIFO, bandwidth) in past jobs.
  • Modeling the algorithm/idea with C++
• Responsible for Image/Video processing IP RTL design and verification.
• Support fullchip integration, maintain chip level c-model to support full chip simulation.
• Co-work with algorithm team, design team, verification team to ensure the chip implementation follows architectural intend.
• Help with chip level RTL design, integration and verification, including FPGA emulation.
• Support FPGA validation and chip validation, customer design-in

Requirements:

• Master/Ph.D Degree in Electrical/Communication Engineering or related fields.
• Minimum 3 years industry SoC development experience. Video processing SoC design experience is preferred.
• In-deep knowledge for Verilog, C/C++
• Excellent C/C++ programming skills required
• Good knowledge for full chip C/C++ project maintain
• Good knowledge for C/C++ hardware modelling skill, effective coding for hardware implementation.
• Familiar with clock, reset, low power design
• Experience in bus (AXI or OCP) fabric development, integration & performance optimization is a plus.
• Experience in Perl/python is a plus.
• Fluent speaking/writing in English and Good communication skill.