Senior/Staff Verification Engineer

Apply Now

Location: Shanghai, China

We are looking for Senior and Staff Verification engineer with SystemVerilog/UVM background. Past experience in video processing SOC verification is a plus.


  • To develop test cases and/ or test framework
  • To develop verification components using System Verilog
  • To execute and debug test cases


  • Bachelor's degree or above in Electrical Engineering, Computer Science, or equivalent education
  • Must have executed at-least 1 ASIC/SoC Verification project entirely
  • At-least 4 years of experience in System Verilog HVL.
  • At-least 3 year of experience in UVM/OVM/VMM.
  • Hands on experience of developing assertion, checkers, coverage and scenario creation
  • Experience in developing test and coverage plan, Verification environment and validation plan.
  • Knowledge of at-least one industry standard protocols like MIPI, HDMI, PCIe, VbyOne, USB or similar is required.
  • Experience in scripting languages (Python, Perl, Linux Shell scripting etc.)
  • Experience with mobile communication standards is an advantage
  • You will have to participate in daily and periodic agile meetings also to do documentation for verification specification and reports.