Senior DFT Engineer
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Location: Shanghai, China
Job Responsibilities:
- Proficiency in whole Chip DFT architecture definition and DFT plan review.
- Be responsible for defining/Implementing different schemes of DFT aspects: including scan insertion, ATPG generation, MBIST insertion, Boundary scan and functional test pattern generation. (Mentor DFT flow is a plus)
- Be responsible for DFT related STA; work with BE, analog team and third party to drive full chip P&R and timing closure.
- Experience with pre and post RTL/netlist simulation, good debug capability; familiar with Verilog.
Preferred Experience:
- ATE on-line debugging background is a plus.
- Experience with 28/22/12 nm process is a plus; and/or several chip sign-off.
- Familiar with the rtl design or have experience of rtl design is a plus.
- Familiar with logic synthesis, Formal Verification flow.
- Strong problem solving skills; self-motivated and good team player; can take international business trip if needed.
- At least 3 years working experience.