Senior/Staff IC Integration Engineer

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Location: Shanghai, China


  • SoC integration design flow include synthesis, lower power design and timing/formal/lint sign-off on 28nm or more advance process nodes
  • Sub-unit integration flow also includes synthesis, low power design, and timing/formal/lint sign-off
  • Drive and support the SoC physical implementation at both die and package level
  • Work on synthesis flow development and execution on large scale, multi-level hierarchy SoC design
  • Work on formal, low power design flow development and execution on multi power domain SoC design
  • Candidate will be exposed to entire IC integration flow, helping integrate various IPs into a multi-million gate SoC for leading edge customer and mobile electronics


  • Experience with one of or more of the following
    • Synthesis and Low power design flow building and execution
    • STA timing analysis, power analysis, or Formal analysis
    • Pre and post RTL/netlist simulation, with good debug capability and familiarity with Verilog design language
    • Standard cells and sram integration at 40nm and below process technology; Advanced process nodes such as finfet or FDSOI will be a bonus
  • Good understanding of STA timing sign-off and SDC constraints
  • Good understanding of UPF/CPF
  • Good at TCL/Perl/Makefile scripting language
  • RTL coding experience for digital logic design will be a plus
  • Familiarity with physical design flow and impact on large scale SoC design will be a bonus
  • Familiarity with DFT and SoC structure testing methodology will be a plus
  • Excellent team player, who is willing to work on multiple tasks with members from across IC design team
  • Fluent in oral and written English
  • 3~5 years of work experience in STA, Formal analysis, chip/IP synthesis

Education Requirement:

  • Required: Bachelor's, Electrical Engineering
  • Preferred: Master's, Electrical Engineering