ASIC Architect

Location: Shanghai, China


  • Responsible for SoC architecture development to achieve good area/power/performance
  • Collaborate with Marketing and System team to define chip specifications and product roadmaps
  • Co-work with algorithm team, design team, verification team to ensure the chip implementation follows architectural intend
  • Help with chip level RTL design, integration and verification, including FPGA emulation
  • Maintain chip level c-model to support full chip simulation
  • Support product validation, ATE test and other chip level issues during high volume ramp-up


  • Master/Ph.D Degree in Electrical/Communication Engineering or related fields\nMinimum 3 years industry SoC development experience. Video processing SoC design experience is preferred
  • Fluent in Verilog, C/C++
  • Familiar with clock, reset, low power design
  • Experience in bus fabric development, integration & performance optimization
  • Familiar with OCP protocol is a plus
  • Experience in Perl/python is a plus
  • Fluent speaking/writing in English and Good communication skill
  • Self-motivated, Organized, Team Player, Result Oriented, and Fast learning on challenging task