Senior IC Engineer (a)

Location: Shanghai, China


  • Independently handle key IC design tasks: Comprehend algorithm or transaction protocol specifications
  • Develop block-level micro-architecture and implementation with RTL
  • Preparation of technical documentation
  • Co-development of verification plan and test case definitions
  • Chip- and block-level verification debug
  • Subsystem- and SoC-level integration, including timing constraint definition, logic synthesis, power analysis and timing closure
  • Support FPGA validation and silicon bring-up
  • Interface with 3rd party vendors for successful IP integration into SOC


  • BSEE Degree or above
  • 3 to 5 years of hands-on experience in digital IC design
  • Familiar with ASIC design methodology and SoC implementation flow
  • Experience with common digital IC design CAD tools for simulation, logic synthesis, formal verification and static timing analysis
  • Attention to detail, self-motivated and the ability to be a team player while working independently
  • Strong analytical and problem-solving skills
  • Good communication skills and proficient in written and verbal English
  • Working experience in one of the following areas is a plus:
    • Image or video processing IP design
    • Computer architecture
    • Interface controllers such as DDR, MIPI, PCI-Express, SATA, USB and HDMI
    • Mobile or low-power SoC design
    • Scripting languages such as bash/csh, Perl or Python